Manuela Junghähnel, Fraunhofer IZM-ASSID, Moritzburg, Germany
As semiconductor devices push beyond the limits of traditional scaling, advanced packaging has emerged as a decisive enabler for next generation performance, functionality, and system integration. Heterogeneous Integration combining chiplets, high density interconnects, and diverse materials within a unified package demands manufacturing technologies that deliver exceptional precision, scalability, and material flexibility. PVD has become a cornerstone in this landscape, providing critical thin film layers that define electrical performance, reliability, and thermal behavior in “state of the art” packaging architectures.
This presentation highlights how innovations in PVD process engineering are accelerating the evolution of advanced packaging. Key focus areas include high‑density redistribution layers (RDL), advanced UBM and seed layers for fine‑pitch interconnects, diffusion barriers for copper metallization, and conformal coatings required for through‑silicon vias (TSVs). Emerging requirements such as larger panel formats, ultra‑low‑defect metallization, and tight uniformity control across increasingly complex topographies are driving the development of new plasma‑enhanced, reactive, and high‑throughput PVD approaches.
Moreover, the role of PVD in enabling large‑area advanced packaging and integrated photonics will explore, where film stress control, adhesion engineering, and optical‑grade metal deposition are critical. As AI, high‑performance computing, and edge devices demand unprecedented integration density, PVD‑based materials and process innovations are becoming essential to building chip and chiplet systems of the future. The presentation gives insight into current challenges, industrial trends, and forward‑looking process strategies that position PVD as a key technology for enabling the next era of heterogeneous integration.