Sumit Goswami, Khosrow Namjou Khaless, Md Koushik Alam, Preston Larson, Gang Yang, Binbin Weng, University of Oklahoma, Norman, OK
Silicon nanostructures are critical in driving Mid-Wave Infrared applications, ranging from environmental sensing, medical diagnostics, free-space communication, nonlinear photonics, and many more. Post-lithography, reactive ion etching (RIE) is widely considered the “gold standard” for achieving high-aspect-ratio (HAR) silicon nanostructures with vertical sidewalls. Commonly used RIE recipes for silicon involve chemically reactive plasmas generated from gases such as SF₆, CF₄, and CHF₃. Several shortcomings, such as a strong affinity towards isotropic etching in SF₆ plasma and significant polymer buildup in the chamber with CF₄ and CHF₃ plasmas, often plague these processes. To circumvent this issue, Nguyen et al. in J. Vac. Sci. Technol. A 38, 053002 (2020) demonstrated a clever cycling recipe termed CORE (meaning clear, oxidize, remove, and etch), similar to the BOSCH process but without the need for costly fluorocarbon inhibitor (C4F8). The CORE recipe uses a combination of silicon surface oxidation (to protect the sidewalls) and a mild SF₆ plasma (to remove and etch the silicon) in a cyclic process to achieve HAR structures. However, the need for complex apparatus, such as fast-switching mass flow controllers (MFCs), significantly increases overall operational costs. Additionally, the CORE recipe results in a noticeable undercut at the bottom of the Chrome (Cr) mask, which can be problematic during device fabrication.
Here, we will present a systematic approach to optimizing the CORE process for silicon in a basic Trion ICP-RIE system. First, we fabricated a 2D periodic lattice of dot arrays on a photoresist-covered silicon substrate using Laser Interference Lithography (LIL), a low-cost, high-throughput, maskless alternative to established lithography techniques such as electron beam lithography (EBL) and direct laser writing. After that, we applied a Chrome mask to selectively protect against etching during the fabrication of silicon nanostructures. We then optimize the time and power of the oxidize, remove, and etch steps to achieve a smooth sidewall with ~93° sidewall angle. To reduce the mask undercut effect in the CORE process, we developed a strategy to vary the duration of the “etch” step and the number of cycles for a given duration of the “etch” step. We experimentally show that silicon nanostructures comprising a 2D periodic lattice of nanopillars with long-range nanohole arrays exhibit broadband near-zero reflectance over the wavelength range 1.8-3.2 µm. These unconventional silicon nanostructures, fabricated using the multibeam LIL method, could be extremely useful for mid-IR anti-reflection coating applications.