Robert Mroczyński¹, Mirosław Puźniak^1,2, Wojciech Gajewski², Marcin Żelechowski^2
1Warsaw University of Technology, Warsaw, Poland
²TRUMPF Huettinger Sp. z o.o., Zielonka, Poland
This work's main aim was to develop the technology of thin hafnium oxynitride layers employing the High-Impulse Power Magnetron Sputtering (HiPIMS) method with improved electrical parameters. The optimization procedure was implemented using the Taguchi orthogonal tables. During the optimization procedure, the parameters of examined dielectric films were monitored employing optical methods (spectroscopic ellipsometry and refractometry), electrical characterization (C-V and I-V measurements of MOS structures), and structural investigations (AFM, XRD, XPS). The thermal stability of fabricated H_fO_xN_y layers up to 800 °C was also examined. The presented results have shown the correctness of the optimization methodology as HfOxNy layers formed using optimal HiPIMS process are characterized by improved electrical parameters, which is revealed in lower flat-band voltage (Vfb) values, the disappearance of frequency dispersion of C-V characteristics, reduced effective charge (Qeff/q), and interface traps (Ditmb) densities of examined MOS structures. It is worth underlying that the improved electrical properties can correlate with the lower nitrogen content in the layer bulk and at the semiconductor-dielectric interface. Moreover, the superior stability of H_fO_xN_y layers up to 800 °C was proved, and no deterioration of electrical properties or surface morphology has been noticed. However, a slight increase of crystalline phase in the layer bulk was observed. The examinations of H_fO_xN_y layers revealed comparable electrical properties and higher immunity to thermal treatment of dielectric films formed using HiPIMS compared to the standard Pulsed Magnetron Sputtering technique. Finally, we successfully applied HiPIMS HfOxNy films as gate dielectric films in MOSFET devices. The fabricated structures revealed improved electrical properties compared to FET structures based on silicon dioxide (SiO₂) gate dielectric layers.